Spurious performance is often a challenging specification to achieve in direct digital synthesizers (DDS). Digital to analog converters (DAC) based DDS are limited by the resolution of the DAC, and digital to time converter (DTC) based systems are limited by the resolution and error achievable in the output tapped delay line. Improvement in the spurious performance of DTC systems depends on overcoming problems with increasing the accuracy and resolution of the output tapped delay line.
The resolution of the tapped delay line is determined by the minimum delay element used in the output tapped delay line and is often limited by the process technology. For example, a delay line with 32 taps operating at 1 GHz will have a resolution of the period divided by the number of taps or 1 ns/32=31.25 ps. There are ways to improve the resolution by using other configurations such as differential delay lines or locking to multiple wavelengths. However, for practical purposes, a tapped delay line will never have infinite resolution. This finite resolution will limit the accuracy to which the DDS output can place an edge. This phenomenon is called quantization error and it leads to spurious frequency components in the output.
Another source of spurs arises from mismatch errors in the delay line. Mismatch errors between transistors, which are unavoidable in integrated circuits, will cause unequal delays across the delay line and cause errors in the edge placements at the output of the DDS.